1. Field of the Invention
The present invention relates to a pixel device, and more particularly, to utilize the layout technique to increase the capacitance of the storage capacitor included in the pixel.
2. Description of Related Art
Because liquid crystal displays (LCDs) can be made thin, compact, and lightweight, the LCDs are becoming increasingly prevalent in high density projection-type display. The panel of the LCD is composed of a pixel matrix which comprising a plurality of pixel devices. FIG. 1 is a circuit diagram of a conventional pixel device. Referring to FIG. 1, each pixel device has a switch element 110, a storage capacitor 130, and a liquid crystal cell 120. The switch element 110, for example, a transistor which has a gate coupled to a scan line L11 for receiving a scan driving signal, a first source/drain coupled to a data line L12 for receiving a data driving signal, and a second source/drain coupled to an electrode M1 of the liquid crystal cell 120 and an electrode M2 of the storage capacitor 130. The other electrode M3 of the liquid crystal cell 120 and the other electrode M4 of the storage capacitor 130 are respectively coupled to a common voltage Vcom and a reference voltage Vref.
When the scan driving signal is asserted to conduct the switch element 110, the data driving signal with a pixel voltage Vpix can be applied to the liquid crystal cell 120 through the data line L12 and the liquid crystal cell 120 can be responded to the delivered data driving signal and thereby controls the rotation and the light transmission of the liquid crystal. Nevertheless, the applied pixel voltage would decrease between the two electrodes M1 and M3 of the liquid crystal cell 120 due to the leakage current. Hence, the storage capacitor 130 is used to maintain the voltage difference between two electrodes M1 and M3 of the liquid crystal cell 120 during a scan frame time.
The storage capacitor 130 is an important component in the pixel device, and people previously mentioned there are three structures of the storage capacitor 130 according to the layout and process technique, that is, poly-insulator-poly (PIP) structure, metal-insulator-metal (MIM) structure, and metal-oxide-silicon (MOS) structure. FIG. 2A is a circuit diagram of a pixel device. Referring to FIG. 2A, the pixel device 200 includes a switch element 210, a liquid crystal cell 220 and a storage capacitor 230 with PIP structure. The connections between the switch element 210, the liquid crystal cell 220, and the storage capacitor 230 are the same as FIG. 1. FIG. 2B is a layout structure diagram of the storage capacitor 230 in FIG. 2A. Referring to FIG. 2A and FIG. 2B, the electrodes P21 and P22 of the storage capacitor 230 are respectively made by a first poly-silicon layer and a second poly-silicon layer, wherein an insulator IN21 is coupled between the electrodes P21 and P22. Referring to FIG. 2B, the electrode P21 made by the first poly-silicon layer is coupled to an electrode M211 made by a first part of a first metal layer, wherein the reference voltage Vref is provided to the electrode M211. The electrode P22 made by the second poly-silicon layer is coupled to an electrode M212 made by a second part of the first metal layer, wherein the pixel voltage Vpix is provided to the electrode M212. The pixel structure as shown in FIG. 2A and FIG. 2B is capable of applying to an liquid crystal on silicon (LCOS) panel and thereby the pixel electrode M23 of the liquid crystal cell 220, which acts as a metal mirror or a reflector, needs to be coupled to the electrode M212 with the pixel voltage Vpix via an electrode M22 made by a second metal layer.
FIG. 3A is a circuit diagram of another pixel device. Referring to FIG. 3A, the pixel device 300 includes a switch element 310, a liquid crystal cell 320 and a storage capacitor 330 with MOS structure. The connections between the switch element 310, the liquid crystal capacitor 320, and the storage capacitor 330 are the same as FIG. 1. FIG. 3B is a layout structure diagram of the storage capacitor 330 in FIG. 3A. Referring to FIG. 3A and FIG. 3B, the electrodes D31 and P31 of the storage capacitor 330 are respectively made by a diffusion layer and a poly-silicon layer, wherein an insulator IN31 is coupled between the electrodes D31 and P31. Referring to FIG. 3B, the electrode D31 made by the diffusion layer is coupled to an electrode M311 made by a first part of a first metal layer, wherein the reference voltage Vref is provided to the electrode M311. The electrode P31 made by the poly-silicon layer is coupled to an electrode M312 made by a second part of the first metal layer, wherein the pixel voltage Vpix is provided to the electrode M312. Besides, an electrode M33 of the liquid crystal cell 320 is coupled to the electrode M312 with the pixel voltage Vpix via an electrode M32 made by a second metal layer.
FIG. 4A is a circuit diagram of another pixel device. Referring to FIG. 4A, the pixel device 400 includes a switch element 410, a liquid crystal cell 420 and a storage capacitor 430 with MIM structure. The connections between the switch element 410, the liquid crystal cell 420, and the storage capacitor 430 are the same as FIG. 1. FIG. 4B is a layout structure diagram of the storage capacitor 430 in FIG. 4A. Referring to FIG. 4A and FIG. 4B, the electrodes M41 and M44 of the storage capacitor 430 are respectively made by a first metal layer and a capacitor top metal (CTM), wherein an insulator IN41 is coupled between the electrodes M41 and M44. The electrode M44 made by CTM is coupled to the electrode M42 made by a second metal layer, wherein the pixel voltage Vpix is provided to the electrode M42 and the reference voltage Vref is provided to the electrode M41. Besides, an electrode M43 of the liquid crystal cell 420 is coupled to the electrode M42 with the pixel voltage Vpix.
In the complementary metal-oxide semiconductor (CMOS) process, the storage capacitors with PIP structure and MOS structure are often used. The said kinds of storage capacitor are layout in the same plane of the transistor taken as the switch element so that the capacitance of the storage capacitor would drastically decrease when the area of the pixel device is decreased. Besides, single structure, such as PIP structure, MOS structure, or MIM structure, is utilized in the said pixel device. Apparently, the space forming the pixel device can not be utilized efficiently. Hence, how to obtain a maximum capacitance of the storage capacitor in the same area of the pixel device or keep the needed capacitance of the storage capacitor in the situation of decreasing the area of the pixel device is an important issue for study and discussion.